Computer Arithmetic

A binary adder does the same small job at each bit position. It combines the two operand bits with a carry from the position to the right. The meaning of the completed bit pattern comes afterward.

Follow the carry

A half adder has two inputs: its sum is their XOR and its carry is their AND. A full adder also accepts a carry-in:

Here multiplication means AND and addition means OR. The sum is 1 for an odd number of 1 inputs; the carry is 1 for at least two. Chaining full adders makes a ripple-carry adder. Only bit 0 receives the initial carry; every later bit receives the carry produced by its neighbor.

For 23 + 45, write 0001 0111 + 0010 1101. At bit 0, 1 + 1 produces sum 0 and carry 1. At bit 1, 1 + 0 + 1 again produces 0 and carry 1. At bit 2, three 1 inputs produce sum 1 and carry 1. Continuing left gives 0100 0100, or 68, with no final carry.

An n-bit result keeps only the low n bits, so the circuit computes the sum modulo $2^n$. In 8 bits, 1111 1100 + 0000 0101 produces 0000 0001 and carry-out 1. Read as signed, this is −4 + 5 = 1. Read as unsigned, it is 252 + 5 = 257, whose low eight bits represent 1. The circuit has not changed; the permitted range has.

Turn subtraction into addition

Two's complement gives the identity

A subtraction control line XORs every bit of the second operand with 1, inverting it, and sets the initial carry-in to 1. For addition, that line is 0, so the second operand passes unchanged and the initial carry is 0.

To compute 23 − 45, invert 0010 1101 to 1101 0010. Add 0001 0111 + 1101 0010 + 1 to obtain 1110 1010, with carry-out 0. Its signed value is −22. Leaving the initial carry at 0 would give −23: inversion alone supplies one less than the required negative value.

For unsigned subtraction, carry-out 1 means no borrow; carry-out 0 means a borrow was needed. Thus the carry-out 0 in 23 − 45 reports an unsigned result below zero. Arm records this no-borrow carry; x86 records its inverse as the borrow flag.

Match widths before operating

RISC-V lb sign-extends a byte, lbu zero-extends it, and addi sign-extends its 12-bit immediate. Choose extension from the operand's meaning before sending the bits to the adder.

The most negative signed value has no positive partner at the same width. Negating 8-bit 1000 0000 inverts it to 0111 1111 and adds 1, returning 1000 0000. The desired +128 needs a wider signed format.

Overflow means the exact result falls outside the destination's range. Unsigned n-bit values run from 0 through $2^n-1$; signed two's complement values run from $-2^{n-1}$ through $2^{n-1}-1$. Eight bits hold 0 through 255 unsigned, or −128 through 127 signed. The same stored result can be valid in one reading and overflow in the other.

Test the right signal

For signed addition or subtraction, hardware can use

where the two carries enter and leave the sign position. Carry-out alone answers the unsigned question.

Add 107 and 54 in 8 bits: 0110 1011 + 0011 0110 gives 1010 0001. A carry enters bit 7 but none leaves, so overflow is 1. The unsigned value 161 fits; the signed reading −95 does not equal the true sum 161. Conversely, −4 + 5 gives carry 1 but signed overflow 0. Adding 1000 0000 to itself gives carry 1 and overflow 1, so both readings fail.

Adding opposite signs cannot overflow: the exact sum lies between the operands. Subtraction needs its own sign rule because subtracting a negative increases the first operand. For example, 100 − (−40) is too large for signed 8 bits even though both input values fit.

Know what the instruction does

x86 add sets carry and overflow flags. Arm flag-setting operations such as ADDS set them; ordinary ADD preserves the existing flags. MIPS add and addi trap on signed overflow, while addu and addiu do not. RISC-V integer addition writes the low bits and has no overflow flags or arithmetic-overflow trap.

After add t0, t1, t2, an unsigned RISC-V check is:

bltu t0, t1, overflow

A wrapped unsigned sum is smaller than an original operand. Signed values need a different check:

slti t3, t2, 0
slt  t4, t0, t1
bne  t3, t4, overflow

The first instruction records whether the second operand is negative. The second records whether the result is smaller than the first operand. Without overflow these tests agree: adding a negative decreases the value, while adding a nonnegative value cannot decrease it. A mismatch detects overflow. For a known positive immediate, a signed branch testing whether the sum decreased is enough.

Separate hardware from language rules

C and C++ unsigned arithmetic wraps modulo $2^n$; signed overflow is undefined behavior. Java int and long wrap, while Math.addExact reports overflow with an exception. Python integers grow as needed. A hardware wrap therefore does not establish what a C program is allowed to do.

Wrapping additions and subtractions preserve a final result that fits: in 8-bit modular arithmetic, (100 + 50) − 60 wraps first to −106 and then to 90. This reasoning applies to wrapping arithmetic, not C signed expressions that overflow.

Saturation is a different policy. Unsigned 8-bit 200 + 100 saturates to 255 instead of wrapping to 44. It is useful for pixel intensities and other bounded signals, where wrapping a large positive result to a small value would be misleading.

An arithmetic logic unit, or ALU, takes operands and control inputs and produces a result plus status outputs. It is combinational: its outputs depend on the present inputs. Registers hold operands and capture results; the ALU itself stores nothing.

Build one bit, then repeat it

A 1-bit slice computes AND, OR, and a full-adder sum in parallel. A multiplexer selects which candidate reaches the result bit. In an n-bit ALU, all slices share the operation controls, while each adder's carry-out feeds the next slice's carry-in. Logic operations work independently at each position; addition depends on the carry chain.

A Bnegate control both inverts the second operand and sets the carry-in of bit 0. Selecting the adder then computes subtraction. Higher slices take their carry from the preceding slice, not directly from Bnegate. Driving every carry input high would insert extra ones into the calculation.

An Ainvert control can also invert the first operand. Selecting AND with both operands inverted produces NOR by De Morgan's law:

Selecting OR with both inverted produces NAND. In these logic equations, the plus sign denotes OR.

Read a control word

One classic textbook ALU uses the fields Ainvert, Bnegate, and a two-bit Operation selector:

These are the encodings of this particular design. They are internal controls, not RISC-V instruction encodings.

For inputs 0101 and 0011, control 0110 inverts the second input to 1100 and supplies initial carry 1. The adder produces 0010, with carry-out 1: 5 − 3 = 2, with no unsigned borrow. Selecting AND for the original inputs would instead produce 0001. The input values can stay fixed while a control change selects a different result path.

The most significant slice also supplies overflow and comparison information. A reduction of all result bits supplies Zero. Those status outputs let the surrounding processor control test the arithmetic result without storing a second full-width result.

Add shifting beside the adder

A full RISC-V base-integer ALU also needs XOR, unsigned comparison, and shifts. A barrel shifter uses a sequence of multiplexer levels. Each level either passes its input through or shifts by a power of two. A 32-bit shifter has levels for 1, 2, 4, 8, and 16 positions, so it handles any shift from 0 through 31 in five levels.

To shift by 13, select the levels for 8, 4, and 1. The selected shifts compose into one result. A logical right shift inserts zeros. An arithmetic right shift replicates the sign bit, preserving a negative value's sign. Thus 1111 0000 shifted right by two gives 0011 1100 logically and 1111 1100 arithmetically.

Comparisons often reuse subtraction. Equality asks whether the difference is zero. Ordering asks whether the mathematical difference is negative, which needs extra care when a fixed-width subtraction overflows.

Detect equality across every bit

The Zero output is the NOR of all result bits:

One nonzero result bit makes Zero false. Subtracting two equal bit patterns produces zero; two distinct n-bit patterns cannot differ by a nonzero multiple of $2^n$, so wrapped subtraction does not create a false equality. An alternative equality circuit XORs corresponding operand bits and tests whether every XOR result is zero.

Correct the sign for signed less-than

RISC-V slt writes the full-width integer 1 if the first signed operand is smaller, or 0 otherwise. In a sliced ALU, the most significant slice computes a Set signal and sends it back to bit 0's Less input. All higher result bits are forced to zero.

The correct Set signal is

When there is no overflow, the sign of the difference works directly. When there is overflow, that sign is reversed relative to the true difference, so XOR with 1 corrects it.

Compare 7 with −8 in four bits. The subtraction 0111 + 0111 + 1 gives 1111. Its sign suggests a negative difference, but the exact difference is 15, outside the range −8 through 7. Overflow is 1, so the corrected Less signal is 1 XOR 1 = 0. The slt result is 0000, correctly reporting that 7 is not smaller than −8.

Use borrow for unsigned less-than

Unsigned comparison uses a different signal:

for subtraction performed with inverted second input and initial carry 1. Carry-out 0 means a borrow was needed, so the first unsigned operand is smaller.

This distinction appears in slt versus sltu, and in the branches blt versus bltu and bge versus bgeu. Neither the result's sign alone nor a generic “negative flag” answers both questions.

Apply the comparison in software

An unsigned bounds check can reject negative indices as well as indices at or above the array length:

bgeu x10, x11, IndexOutOfBounds

Here x10 holds the signed index and x11 holds a nonnegative length that fits in the signed range. A negative index, reinterpreted as unsigned, is at least $2^{n-1}$ and therefore exceeds every such length. The length condition matters: it makes one unsigned comparison sufficient.

Language conversions can change comparison meaning too. With a 32-bit C unsigned int, -1 < 0u is false because −1 converts to 4,294,967,295 before comparison. Trace the conversion before reasoning from the written minus sign.

A ripple adder's carry has to cross each bit in order. Carry lookahead replaces that serial wait with logic that predicts carries from operand bits and the initial carry.

Describe each bit's carry behavior

Let generate and propagate be

These are Boolean expressions: multiplication is AND and addition is OR. Generate is 1 when the bit creates a carry regardless of the incoming carry. Propagate is 1 when an incoming carry can pass through. The recurrence is

A bit with both inputs 1 generates a carry; a bit with one input 1 passes a carry; a bit with both inputs 0 stops it. With this OR definition, a generating bit also has propagate 1, which does not change the carry formula.

Expand the dependency

Substitute the expression for each previous carry:

Each expression now depends on operand-derived signals and the initial carry, not a serial chain of intermediate carry outputs. Once the carries are available, each sum bit is still the XOR of its two inputs and carry-in.

For 1011 + 0110 with initial carry 0, generate from bit 0 upward is 0, 1, 0, 0 and propagate is 1, 1, 1, 1. Thus the carries into bits 1 through 4 are 0, 1, 1, 1. The four result bits are 0001 with carry-out 1, representing 11 + 6 = 17.

Build groups instead of giant gates

A four-bit block has group signals

Its output carry is $G+P{c}_0$. A second lookahead level combines these block signals using the same rule. Four four-bit blocks and a group-lookahead unit make a 16-bit adder. Further grouping supports wider designs; parallel-prefix adders such as Kogge–Stone organize these relationships into a fast network.

In a simple gate-delay model, a ripple carry costs about two gate delays per bit, or 32 for 16 bits. A two-level lookahead design can deliver the last carry in about five: one for bit signals, two for group signals, and two for the group carry. This estimate counts logic levels and assumes the required gates; actual delay also depends on gate size and wiring. Grouping trades more hardware for a carry path that grows roughly logarithmically with width.

A carry-select adder spends area differently: it calculates an upper block twice, once for carry-in 0 and once for carry-in 1. A multiplexer selects the correct result when the lower block's carry arrives.

Some adders define propagate with XOR instead of OR. That also gives correct carries, and makes the sum $s_i=p_i\oplus c_i$. Keep the chosen definition consistent when deriving group logic.

Each binary multiplier bit chooses a shifted copy of the multiplicand or zero. Adding those partial products gives the result. An n-bit operand times an m-bit operand can require n + m bits, so two 32-bit operands need a 64-bit full product.

Trace shift-and-add

For n-bit unsigned operands, initialize a 2n-bit product to zero. Repeat n times: test the multiplier's low bit, add the current multiplicand if that bit is 1, shift the multiplicand left, and shift the multiplier right. The multiplicand register must be wide enough to retain its shifted copies.

For four-bit 6 × 5, the multiplier is 0101:

The final product is 30. The bit being tested and the shift direction work together: testing the high bit while shifting the multiplier right would pair bits with the wrong weights. This sequential design takes n steps, including steps whose multiplier bit is zero.

Share register space

The first design uses a 2n-bit multiplicand register and adder. A refined design keeps the multiplicand fixed in n bits, puts the multiplier in the low half of a 2n-bit product register, and starts the high half at zero.

When the low bit is 1, add the multiplicand into the high half. Keep the adder's carry-out in one extra bit, then shift that carry and both product halves right together. The multiplier bits leave from the right as product bits occupy the space they free. Dropping the carry breaks large products: with four-bit operands, 15 × 15 would incorrectly become 1 instead of 225. At one step per clock, the simple 32-bit implementation takes about 32 cycles.

Keep the product width in view

An unsigned product fits in n bits exactly when its full product's upper n bits are zero. For 6 × 5, the full result is 0001 1110; storing only 1110 gives 14. The multiplication itself was correct, but the narrow destination discarded part of it.

A left shift by k multiplies by $2^k$ when the result fits. Multiplication by 8 becomes a shift by three; multiplication by 10 can use two shifted copies:

(x << 3) + (x << 1)

The arithmetic is $8x+2x=10x$. Width and programming-language rules still apply to the shifts and addition; this rewrite does not create more result bits.

Read the RISC-V result halves

mul returns the low XLEN bits, where XLEN is the integer register width. mulhu returns the high half for unsigned operands. The signed high-half instructions are mulh for two signed operands and mulhsu for a signed first operand and unsigned second operand.

Software requesting the full product can issue the appropriate high-half instruction followed by mul with the same operands. An implementation may fuse the pair. The low result alone cannot establish that an unsigned product fits; the upper half supplies that evidence.

Signed multiplication must handle the operand signs without losing the most negative value. Faster hardware also needs a way to reduce many partial products without waiting for a full carry-propagating addition each time.

Multiply magnitudes safely

One approach records the signs, forms unsigned n-bit magnitudes, multiplies them into 2n bits, and negates the full product if exactly one operand was negative. For four-bit −8, the magnitude bits 1000 represent unsigned 8. They cannot be read as a positive four-bit signed value.

The low n product bits are identical for signed and unsigned interpretations. 1111 × 0010 gives unsigned 30 (0001 1110) or signed −2 (1111 1110). Both low halves are 1110; only the upper halves differ. This is why one mul instruction serves both interpretations.

Follow Booth's decisions

Booth's algorithm works directly with two's complement. Give the accumulator n + 1 bits and sign-extend the multiplicand to that width, so both it and its negative fit. Initialize the accumulator to zero, place the multiplier in its n-bit register, and append one extra bit initialized to zero.

Examine the multiplier's low bit and the appended bit as a pair:

After each decision, shift the entire accumulator–multiplier–extra-bit register right arithmetically. Repeat n times; discard the appended bit and the accumulator's redundant top sign bit to obtain the 2n-bit product.

For 2 × (−3), use multiplicand 00010, multiplier 1101, and accumulator 00000. The pairs are 10, 01, 10, 11. After the respective operations and shifts, accumulator and multiplier are 11111 0110, 00000 1011, 11111 0101, and 11111 1010. The low eight product bits 1111 1010 represent −6.

A logical shift would insert zero at the top and corrupt negative partial results. The extra accumulator bit also matters: subtracting a most-negative n-bit multiplicand needs a positive value unavailable in n signed bits.

Reduce the work and the carry paths

Booth recoding replaces a run of 1s with a subtraction at its low end and addition above its high end. For example, 126 is 128 − 2. Alternating bits may offer no saving. Radix-4 Booth examines two multiplier bits per step and uses digits from −2 through +2, reducing the number of partial products.

A fast multiplier forms partial products in parallel. A carry-save adder compresses three words into two without propagating carries across the word. Wallace or Dadda trees repeat that reduction, then use one final carry-propagating adder. Reducing 32 rows to two takes eight carry-save levels. Pipelining allows several products to be in flight; accepting one every cycle does not mean each finishes in one cycle.

For a signed result narrowed to n bits, every upper-half bit must equal the low half's sign bit. Four-bit −8 × −1 gives full product 0000 1000. The upper half is zero but the retained sign bit is 1, so +8 does not fit the signed destination.

Division produces a quotient and remainder linked by

For a nonzero unsigned divisor, the remainder is nonnegative and smaller than the divisor. An n-bit dividend and divisor need an n-bit quotient and remainder.

Produce the quotient one bit at a time

Read dividend bits from the most significant end. Double the partial remainder, bring in the next bit, and test whether the divisor fits. Subtract it and write quotient bit 1 if it does; otherwise keep the partial remainder and write 0.

For 0111 divided by 0010, the brought-down partial remainders are 0, 1, 3, and 3. The first two are smaller than 2, so their quotient bits are 0. Each 3 permits a subtraction, leaving remainder 1 and quotient bit 1. The quotient is 0011 and the remainder 0001: 3 × 2 + 1 = 7.

Restoring division tries subtraction first. If the trial result is negative, add the divisor back and write 0; otherwise keep it and write 1. Detect failure with a borrow or an n + 1-bit signed difference. An n-bit sign test is unsafe: four-bit 0 − 9 wraps to 0111, whose top bit is 0 despite the borrow.

Compact hardware puts the dividend in the low half of a 2n-bit register and partial remainder in the high half. It shifts left each step and inserts quotient bits on the right. At completion the high half holds the remainder and the low half the quotient.

Nonrestoring division carries a negative trial result forward and adds the divisor during the next step instead of restoring immediately. A final negative partial remainder needs one last add-back. SRT division selects several quotient bits per step using leading divisor and remainder bits; missing entries in such a selection table caused the 1994 Pentium FDIV bug. Division remains dependent on each preceding partial remainder.

Apply truncating signed division

Divide magnitudes, negate the quotient if signs differ, and give a nonzero remainder the dividend's sign.

These results truncate the quotient toward zero and preserve the division identity. RISC-V, Java, and C since C99 use this rule. Python // rounds down instead: -7 // 2 is −4 and -7 % 2 is 1.

Handle exceptional inputs

RISC-V division by zero returns an all-ones quotient and the original dividend as remainder. The signed overflow case, most-negative divided by −1, returns the most-negative quotient and remainder zero. Neither case traps. x86 raises a divide-error exception for both. Software that must report errors checks zero first and also checks the signed overflow pair.

A logical right shift divides unsigned values by powers of two, rounding down. An arithmetic shift rounds negative values down too: −5 shifted right by one becomes −3, while truncating division by 2 gives −2. To implement truncation with a shift, add $2^k-1$ to a negative input before shifting right by k. For −5 and k = 1, shift −4 to obtain −2.

A normal binary floating-point value has the form

The significand is the full value 1.f; the stored fraction contains only f. Normalization guarantees the leading 1, so omitting this hidden bit gains one bit of precision.

Read the three fields

IEEE 754-2019 defines these formats. Single and double precision usually mean binary32 and binary64. The stored order is sign, exponent, fraction. For a normal value, subtract the bias from the unsigned exponent field:

Fraction means the binary fraction after the point, not its bits read as an integer. In binary32, exponent fields 1 through 254 encode exponents −126 through 127. Fields 0 and 255 have special meanings.

A bias makes larger exponents have larger unsigned fields. For positive finite numbers, unsigned ordering of the complete patterns follows numerical ordering. Negative values and NaNs require additional handling.

Encode and decode

To encode −0.75, write its magnitude as ${0.11}_2={1.1}_2\times 2^{-1}$. The sign is 1 and the exponent field is −1 + 127 = 126, or 01111110. Drop the hidden leading 1 and pad the fraction with zeros. The fields are 1 01111110 10000000000000000000000, giving 0xBF400000. In binary64 the same value is 0xBFE8000000000000.

To decode 0x41460000, split it into 0 10000010 10001100000000000000000. The exponent field is 130, so the true exponent is 3. The significand is

Multiplying by 8 gives 12.375. Writing the hidden 1 into the stored fraction would change the value; storing −1 directly in the exponent field would lose the bias rule.

Distinguish range from precision

binary32 reaches approximately $3.40\times {10}^{38}$, with smallest positive normal $2^{-126}$ and about seven significant decimal digits. binary64 reaches approximately $1.80\times {10}^{308}$, with smallest positive normal $2^{-1022}$ and about 15–16 significant digits. binary16 has maximum 65,504, smallest positive normal $2^{-14}$, smallest positive subnormal $2^{-24}$, and about 3.3 significant decimal digits.

Precision counts significant digits, not digits after the decimal point. For example, binary32 stores 1,234,567.89 as 1,234,567.875.

Within the binary32 interval from $2^e$ up to $2^{e+1}$, adjacent normal values are spaced $2^{e-23}$ apart. This spacing is an ulp, a unit in the last place. Just above 1 it is $2^{-23}$, often called machine epsilon. At $2^{24}$ the spacing becomes 2, so 16,777,217 is missing even though much larger numbers fit. More exponent bits widen the scale range; more fraction bits place representable values closer together at a given scale.

Reserved exponent patterns let IEEE 754 represent values beyond ordinary normalized numbers. Always classify the fields before applying a value formula.

Recognize the reserved patterns

binary32 has +0 at 0x00000000 and −0 at 0x80000000. They compare equal, but division can reveal the sign: 1 divided by +0 gives +∞, while 1 divided by −0 gives −∞. A tiny negative result that rounds to zero becomes −0.

Positive infinity is 0x7F800000; the largest finite positive value is 0x7F7FFFFF. Under round to nearest, arithmetic overflow returns a signed infinity. Dividing a finite nonzero value by zero also returns signed infinity, with a different exception flag. Later arithmetic handles infinity consistently: adding 1 to +∞ leaves +∞, multiplying it by −2 gives −∞, and its reciprocal is +0.

Distinguish NaN from infinity

Operations such as zero divided by zero, infinity minus itself, zero times infinity, and the real square root of −1 have no meaningful numerical result. They produce NaN, “Not a Number,” and signal invalid operation.

NaN is unordered: equality and ordered less-than or greater-than tests involving it are false, while inequality is true. In particular, x == NaN cannot detect NaN. Use isnan(x). Quiet NaNs normally propagate through arithmetic; signaling NaNs raise invalid when consumed. In these binary formats the top fraction bit distinguishes a quiet NaN. RISC-V's canonical binary32 quiet NaN is 0x7FC00000.

Approach zero gradually

A subnormal has no hidden 1. Its exponent is fixed at the smallest normal exponent:

For binary32, 0x00000001 is $2^{-149}$ and 0x00400000 is $2^{-127}$. For binary64 the smallest positive value is $2^{-1074}$. Using exponent minus bias with a zero exponent field would be off by a factor of two, even before a mistaken hidden 1 was added.

Subnormals provide gradual underflow: precision decreases as values shrink, with fixed absolute spacing near zero. Distinct finite values in one format still have a nonzero representable difference. Flush-to-zero modes discard that protection and can speed up subnormal handling on some processors.

Read the exception flags

IEEE 754 defines invalid operation, division by zero, overflow, underflow, and inexact. Default handling returns a result and records status; it need not stop execution. Inexact means the rounded result differs from the exact result.

Under default handling, underflow requires both tininess and inexactness. In binary32, $2^{-126}\mathrm{/}2=2^{-127}$ is an exact subnormal and does not raise underflow. RISC-V records NV, DZ, OF, UF, and NX in fflags within fcsr, and floating-point exceptions do not trigger arithmetic traps. A returned infinity alone does not identify whether overflow or division by zero occurred; inspect the flag.

Floating-point arithmetic works on significands and exponents separately. The final result must be the exact operation rounded to the destination format, so intermediate bit movement must preserve enough information for that last decision.

Add with a shared exponent

Addition follows four stages: align, operate, normalize, round. Compare exponents and shift the smaller operand's significand right by their difference. Add magnitudes for equal signs; subtract magnitudes for opposite signs. Shift the result into normalized form and adjust its exponent. Then round, renormalizing again if rounding creates a carry.

Use four-bit significands to see 0.5 + (−0.4375):

1. Write the operands as ${1.000}_2\times 2^{-1}$ and $-{1.110}_2\times 2^{-2}$.
2. Align the second to $-{0.111}_2\times 2^{-1}$.
3. Subtract the magnitudes: ${1.000}_2-{0.111}_2={0.001}_2$.
4. Normalize to ${1.000}_2\times 2^{-4}$, or 0.0625. No nonzero bits were lost, so no rounding change is needed.

Cancellation can require a large left-normalizing shift. Hardware uses an exponent subtractor, an alignment shifter, a significand adder, a leading-zero counter, and normalization and rounding logic. Floating-point adders are commonly pipelined across several cycles.

A decimal model shows why extra digits matter: with four significant digits, 99.99 + 0.161 aligns as $9.999+0.01610$ at scale ${10}^1$. The exact intermediate is 10.01510 at that scale. Normalize to $1.00151\times {10}^2$ and round to $1.002\times {10}^2$. Cutting off the aligned addend too early would lose information needed to choose 100.2.

Multiply scales and significands

Multiply the significands, add the true exponents, and XOR the signs. With biased fields, subtract the bias once:

before normalization adjustments. Two normal significands multiply to a value from 1 up to 4, so their product needs at most one right-normalizing shift. Rounding can require a further adjustment; exponent limits also need checking.

For 0.5 × (−0.4375), binary32 exponent fields give 126 + 125 − 127 = 124, or true exponent −3. The significand product is ${1.000}_2\times {1.110}_2={1.110}_2$. Sign XOR is 1, giving $-{1.110}_2\times 2^{-3}=-0.21875$.

Round once with fused multiply-add

FMA computes a × b + c with one rounding after the full expression. Separate multiplication and addition round twice. In binary32, take $a=1+2^{-23}$, $b=1-2^{-23}$, and c = −1. Their exact product is $1-2^{-46}$. A separate multiply rounds this to 1, so the addition returns zero. FMA retains the small product difference and returns $-2^{-46}$.

RISC-V F supplies 32 floating-point registers, f0 through f31; D widens the same bank for double precision. flw/fsw and fld/fsd transfer values. Arithmetic includes fadd.s, fmul.s, fdiv.s, and fsqrt.s, with .d forms for double precision. fmadd.s computes fused multiply-add. Comparisons such as flt.s write 0 or 1 to an integer register, and fcvt converts formats or integer values.

A finite format cannot store every exact result. Correct rounding means choosing the representable result required by the rounding direction, as if the operation had first been computed exactly. Basic arithmetic, square root, and FMA obey this rule. NaN payload and sign bits need not be identical across processors.

Choose a rounding direction

The first four are required for binary implementations; ties to even is the default. Ties away is required for decimal formats, and RISC-V also supplies it for binary operations. Its names are RNE, RUP, RDN, RTZ, and RMM; an instruction can select a mode directly or use the dynamic mode in fcsr.

For ties to even rounded to whole numbers, 2.5 becomes 2 and 3.5 becomes 4. In binary with four-bit significands, ${1.0011}_2$ rounds to ${1.010}_2$, and ${1.0101}_2$ also rounds to ${1.010}_2$. The even bit belongs to the retained significand, not the exponent or a printed decimal digit.

Keep guard, round, and sticky information

After normalization, keep two additional bits beyond the destination significand: guard and round. The sticky bit is the OR of every later discarded bit. It records whether that entire tail is zero.

For nearest rounding, guard 0 means below halfway. Guard 1 with round or sticky 1 means above halfway. Guard 1 with both later indicators 0 means an exact tie. At a tie, increment the retained significand only if its current low bit is 1.

For a four-bit-significand sum of 8 + 0.5625, alignment gives

Retain 1.000; guard is 1, round is 0, and sticky is 1 because the remaining tail contains a 1. The value is above halfway, so increment to ${1.001}_2\times 2^3=9$. Discarding sticky would falsely make this a tie and choose 8.

A sticky bit is evidence about all lost bits, not simply the third bit after the retained portion. During shifting, once any lost bit is 1, the sticky state stays 1 for that accumulated tail.

Interpret error and overflow

For finite results within range, nearest rounding has absolute error at most half an ulp; directed rounding has error below one ulp. For normal binary32 results, the usual nearest-rounding relative bound is $2^{-24}$; for binary64 it is $2^{-53}$. Subnormal results need absolute-error reasoning because their relative precision declines.

Rounding direction also controls overflow results. Positive overflow gives +∞ under nearest or toward-positive rounding, but the largest finite positive value under toward-zero or toward-negative rounding. Negative overflow gives the mirrored behavior.

Integer conversions have their own rules. In C, representable casts such as (int)2.7 and (int)-2.7 truncate to 2 and −2, independently of the current floating-point rounding direction. Check destination range as well as the discarded fractional part.

Floating-point errors often follow directly from finite spacing. Separate the error already present in stored operands from the rounding performed by an operation and from information lost during conversion.

Identify representation error

A reduced fraction has a finite binary expansion exactly when its denominator is a power of two. Values such as 0.5, 0.25, and 0.375 are exact. The expansion of 0.1 repeats, so binary32 stores 0x3DCCCCCD, about 0.10000000149011612. binary64 also stores an approximation.

Consequently, binary64 0.1 + 0.2 produces 0.30000000000000004, different from the stored value nearest 0.3. A short printed result such as 0.1 can be the shortest decimal that round-trips to the same stored bits; it does not establish exactness.

For approximate finite results, use a problem-chosen tolerance, for example

The absolute tolerance handles values near zero; relative tolerance scales with magnitude. The tolerances should reflect the calculation and acceptable error, not just the number of digits printed.

Watch addition lose a small input

Absorption occurs under nearest rounding when a small addend cannot move a large operand to its next representable neighbor. In binary32, 16,777,216 + 1 rounds back to 16,777,216: the neighboring values are two apart, and this tie selects the even significand. A float counter adding 1 can therefore stop progressing.

Changing addition order can change the answer. With binary32 x = −1.5 × 10³⁸, y = 1.5 × 10³⁸, and z = 1, (x + y) + z gives 1. But y + z rounds to y, so x + (y + z) gives zero. Addition is not associative. Parallel reductions may change their grouping when the thread count changes, affecting the final bits.

Repeated rounding also accumulates: adding binary32 0.1 ten million times into a binary32 total gives 1,087,937 instead of 1,000,000. A wider accumulator reduces rounding loss. Adding smaller magnitudes together first can also preserve contributions that a large running total would absorb.

Separate cancellation from inexact subtraction

Cancellation removes shared leading digits from nearly equal operands. The subtraction itself can be exact while earlier operand errors become large relative to the small answer. In binary32, 1.0000001 is stored as $1+2^{-23}$. Subtracting 1 gives about $1.1920929\times {10}^{-7}$ instead of $1.0\times {10}^{-7}$, roughly 19% relative error.

Check conversions and format choices

binary64 exactly represents every 32-bit integer. binary32 does not: 16,777,217 rounds to 16,777,216 under ties to even. Above $2^{53}$, binary64 also misses some integers. Converting a floating-point value to a smaller integer type can exceed its range entirely.

In Ariane 5's 1996 first flight, an out-of-range conversion from 64-bit floating point to a 16-bit signed integer shut down the inertial reference systems and contributed to the loss of the rocket. In the 1991 Patriot failure at Dhahran, a chopped fixed-point approximation of 0.1 accumulated about 0.34 s of timing error after about 100 hours, shifting the tracking window about 687 m. This was a fixed-point representation error, not an IEEE floating-point operation.

Choose binary64 for wider general-purpose precision, binary32 when its smaller memory use suits the task, and binary16 or bfloat16 for suitable low-precision workloads. bfloat16 has eight exponent and seven fraction bits. Exact monetary amounts belong in integer minor units or a decimal type.