How Computers Work

A computer accepts input, follows instructions to process it, stores data, and produces output. These roles apply to a laptop and to a controller hidden inside a washing machine. The difference is the task and the equipment attached to it.

Physical parts and programs

Hardware is the physical equipment. Software consists of programs and the data they work on. The CPU is the processor chip, not the whole computer case. A motherboard connects it to RAM, storage, a GPU, power and device ports. The GPU handles drawing and other work that applies similar operations to many values. A phone combines many of these functions in a system on a chip (SoC).

RAM holds instructions and data being used now. A storage drive keeps programs and saved files without power. In a computer described as having 16 GB of memory and a 512 GB SSD, the first capacity describes RAM and the second describes storage. A larger drive does not provide more working RAM.

A program stored as data

The von Neumann architecture has a CPU, main memory holding both instructions and data, input/output devices, and buses connecting them. John von Neumann described this design in the 1945 "First Draft of a Report on the EDVAC." Its central idea is the stored program: instructions are binary values in memory, ready for the CPU to fetch.

Earlier machines such as ENIAC were set up for tasks with switches and cables. Loading a new program lets a stored-program machine change jobs without rewiring. The Manchester Baby ran a program in rewritable electronic memory on June 21, 1948.

Memory does not attach a meaning to each pattern. The byte 01000001 can represent the number 65, the ASCII letter "A", or part of an instruction. What the CPU or program does with the pattern determines its meaning. During an instruction fetch, the CPU treats the fetched pattern as an instruction.

Why the processor can wait

Instructions and data share the route between the CPU and main memory. Memory also supplies them more slowly than the CPU can use them. This restriction is the von Neumann bottleneck. A fast processor can therefore spend time waiting for the next value. Small, fast caches keep useful copies near the CPU and reduce many of these waits.

Small microcontrollers and signal processors often use a Harvard design. Modern general-purpose CPUs combine the ideas: shared main memory, but separate level 1 instruction and data caches.

Computers inside other devices

An embedded system does a dedicated job inside a larger device. A thermostat reads a temperature sensor, processes the reading, and controls heating. Its stored program usually stays in non-volatile memory. The processor, memory and input/output roles are still present, even without a keyboard, screen or full desktop operating system.

A processor needs three things to access memory: a location, the value to transfer, and a command telling memory what to do. Keeping these roles separate makes a bus transaction much easier to follow.

Three roles on a classic system bus

A bus is a shared communication path. In a classic parallel system bus, several wires or circuit-board tracks carry bits at the same time.

An address names a location; it is not the value stored there. Address 200 can hold 7 today and 9 later without changing its address. A useful comparison is a numbered mailbox: the number identifies the box, while its contents can change.

Follow a read and a write

To read address 200, the CPU puts 200, binary 11001000, on the address bus and sends a read command on the control bus. Memory returns the value at that location, here 7, on the data bus. The CPU copies it into a register.

To write 9 at address 201, the CPU puts 201 on the address bus, 9 on the data bus, and a write command on the control bus. Memory replaces the contents of location 201. Sending 201 on the data bus would send the wrong value; the address and the contents have different jobs.

Address width limits the number of locations

With $n$ address bits there are $2^n$ different addresses. If each address names one byte, that is also the number of addressable bytes.

• 16 bits give $2^{16}=65,536$ addresses, or 64 KiB.
• 32 bits give $2^{32}=4,294,967,296$ addresses, or 4 GiB.
• Increasing from 20 to 21 bits doubles capacity from 1 MiB to 2 MiB.

Every extra bit doubles the combinations. Doubling the bit count from 16 to 32 multiplies the location count by $2^{16}$; it does not merely double it. This calculation gives an addressing limit, not the amount of RAM actually installed.

Data width limits each transfer

A 64-bit data path carries 8 bytes in one transfer. An 8-bit path needs four transfers to carry a 4-byte value. Bandwidth measures how much data can move per second:

At 1 billion transfers per second, an 8-byte path carries 8 billion bytes per second, or 8 GB/s. Address width controls how many locations can be named; data width controls how much moves at once.

A CPU's word is its natural working size, commonly 32 or 64 bits. A 64-bit processor does not require every connection to have 64 wires. Its implemented address range can also use fewer than 64 bits.

Modern links keep the same jobs

Memory channels, PCI Express and USB replace one shared bus with several links. PCI Express and USB are serial: bits travel one after another over fast wire pairs. Addresses, values and commands are packed into messages. They still identify a destination, carry contents and coordinate the transfer.

An input device supplies data; an output device presents a result or acts on it. The classification describes the device's role in the system. It does not describe how complicated the device is inside.

Classify the action

Keyboards, cameras, microphones, barcode readers and sensors supply input. Screens, printers, speakers and actuators supply output. An actuator changes something physical, such as opening a valve or turning a motor.

Some devices do both. A touchscreen senses touches and displays images. A headset combines a microphone with speakers. A network adapter sends and receives data. Storage drives also perform reads and writes through I/O controllers, but their main purpose is keeping data, so they form the separate category secondary storage.

A printer can contain a processor that turns a page into printable dots. It remains an output device because of what it does for the computer. A wireless mouse supplies input just as a wired one does.

Turn continuous signals into numbers

Sound and temperature vary continuously: they are analog signals. An analog-to-digital converter (ADC) measures a signal at regular intervals and encodes the samples as numbers. A digital-to-analog converter (DAC) turns digital values into an analog output, such as the signal driving a speaker.

For one audio channel sampled 44,100 times each second with 16 bits per sample:

This is the raw sample data rate. Each second contains 44,100 measurements, and each measurement needs 16 bits. Sampling and encoding let a computer store and process the recording.

Hardware controller, software driver

Devices connect through ports or wireless links such as USB, HDMI, Bluetooth or Wi-Fi. A device controller is circuitry that handles low-level communication and exposes registers the CPU can read or write. A device driver is software that translates OS requests into commands for the device. The controller is hardware; the driver is software.

Let devices ask for attention

With polling, the processor repeatedly checks a status register. This is simple, but a device that is usually idle can cause many checks with no useful result.

With an interrupt, the controller signals when attention is needed. The CPU completes the current instruction in the simple instruction-cycle model, saves the interrupted state, and runs an interrupt handler. It then restores the saved state and continues. A key press or completed disk read can trigger this sequence.

People and many devices act far more slowly than a CPU. A person types only a few characters per second, while a processor can execute billions of instructions per second. Interrupts let the CPU work between events.

For a large transfer, direct memory access (DMA) lets a device or DMA controller move a block directly to or from RAM. The CPU sets up the operation and works on something else. A completion interrupt tells it when the block is ready. DMA removes the need for the CPU to copy every byte; it still participates in arranging and completing the transfer.

A computer's smallest operations come from circuits that switch between two signal levels. A high voltage represents 1 and a low voltage represents 0. These levels stand for bits; a chip does not recognize the meaning of a photo or a sentence.

Gates turn input bits into an output

A transistor acts as an electronically controlled switch. Small groups form logic gates, each with a fixed input/output rule. A truth table lists every input combination and its output. With two inputs there are four combinations; in general, $n$ inputs need $2^n$ rows.

NOT reverses its single input. The two-input gates behave as follows:

AND needs both inputs to be 1. OR needs at least one, including both. XOR needs different inputs. NAND reverses AND; NOR reverses OR. Reading OR as "one but not both" confuses it with XOR.

To evaluate (A AND B) OR (NOT C) for A = 1, B = 0, C = 0, work from the inputs outward. A AND B gives 0. NOT C gives 1. Finally, 0 OR 1 gives 1. Write down the intermediate outputs so the final gate receives the correct inputs.

Gates add binary digits

A half adder takes two bits. Its sum output is XOR and its carry output is AND. For two input 1s, the sum bit is 0 and the carry bit is 1: the two-bit result is 10, meaning 2.

A full adder also accepts a carry from the preceding column. Chaining these circuits lets an ALU add longer numbers. Follow 0110 plus 0011 from the right:

1. The rightmost column gives 1, with no carry.
2. The next column has two 1s: write 0 and carry 1.
3. The next has 1, 0 and carry 1: write 0 and carry 1.
4. The leftmost has 0, 0 and carry 1: write 1.

The result is 1001, or 9. A carry belongs to the next column; dropping it changes the value.

Gates can hold a bit

Feedback means feeding a circuit's output back into its input. Cross-coupled NAND or NOR gates form a latch that holds one bit while power remains on. A flip-flop captures a new bit at a clock edge, keeping updates in step with the processor's clock. Registers use clocked storage circuits. SRAM cache cells use latch-style circuits; DRAM stores charge in capacitors.

NAND and NOR are each universal: either gate type alone can build any logic function. Connecting both NAND inputs to A gives A NAND A, which acts as NOT A.

These are layers of abstraction. Transistors build gates; gates build adders, registers and control circuits; these build a processor that executes instructions. A programmer can use the instruction layer without designing the switches underneath it.

The CPU, or processor, executes a program's instructions. Its control unit directs work, its arithmetic logic unit performs operations, and its registers hold the values needed immediately. A clock coordinates changes in these circuits.

Direct the work and perform it

The control unit fetches an instruction, decodes it and issues control signals. It might tell memory to return a value, select two inputs for the ALU and enable a register to store the result. It coordinates the operation; the ALU does the arithmetic or logic.

ALU operations include addition, subtraction, comparisons, bit shifts and gates such as AND and XOR. Results also update status flags. A zero flag indicates a zero result; a negative flag records a negative result. A branch can test a flag to choose the next instruction.

Registers hold the immediate working state

Registers are very small, fast storage locations inside the processor. A general-purpose register usually holds one word. For example, x86-64 provides 16 general-purpose integer registers, and 64-bit ARM provides 31. Programs use them to keep values close to the ALU.

The textbook processor makes the following roles visible:

MDR is also called the memory buffer register (MBR). CIR is also called the instruction register (IR). Actual chips organize these jobs in more complex ways, but the model lets you follow the movement of an instruction and its data.

The PC holds an address, not a total of instructions completed. A jump can send it backward to repeat a loop. MAR and MDR also differ: an address such as 10 goes into MAR; the value stored at address 10 goes into MDR.

A clock cycle is one timing step

Clock speed counts pulses per second, measured in hertz (Hz). A 3 GHz clock produces 3 billion cycles each second. The duration of one cycle is:

A pulse lets parts of a circuit advance. Some instructions need several timing steps, and modern processors overlap work on several instructions.

More than one processing core

A core has the control, arithmetic, register and cache resources needed to run an instruction stream. Four cores can carry out four streams at once. A program benefits when its work can be divided among them; merely owning four cores does not split every task.

A GPU has many smaller processing units suited to performing similar operations on many data items. Drawing pixels, processing video and some machine-learning calculations have this form. A CPU suits a wider mix of instructions and decisions.

Think of a kitchen: the control unit assigns actions, the ALU performs them, registers hold ingredients at hand, and memory supplies more. The CPU follows bit patterns mechanically; the useful meaning comes from the program.

The fetch-decode-execute cycle connects the processor's parts into a running program. Each cycle brings in an instruction, determines its operation and carries it out. A trace records the changing registers and memory so each result has a visible cause.

Fetch the instruction

In the simple processor, fetch follows this sequence:

1. Copy the PC into the MAR.
2. Put the address on the address bus and send a memory-read signal.
3. Receive the instruction over the data bus into the MDR.
4. Copy it into the CIR.
5. Advance the PC to the next instruction.

In the teaching machine each instruction occupies one location, so the PC increases by 1. A byte-addressed processor advances by the instruction's byte length. During execution the PC already points beyond the fetched instruction.

Decode, then execute

The control unit separates the opcode, which specifies the operation, from the operand, which supplies a value, register or address. It then sends the signals needed to execute the instruction. A load reads data, an add uses the ALU, a store writes data, and a jump changes the PC. Some descriptions call writing the result a separate write-back stage.

Trace a complete program

The teaching machine has one accumulator. Here LOAD, ADD and STORE use memory addresses as operands.

Address  Instruction      Data address  Value
0        LOAD 10          10            7
1        ADD 11           11            5
2        STORE 12         12            0
3        HALT

Start with PC 0. Fetching LOAD 10 moves the PC to 1. Execution puts address 10 in MAR, reads 7 through MDR, and sets ACC to 7. The operand 10 names a location; it is not the value loaded.

Next, ADD 11 is fetched and PC becomes 2. Memory location 11 supplies 5. The ALU adds 7 and 5, leaving ACC 12. Fetching STORE 12 advances PC to 3. Execution places address 12 in MAR and value 12 in MDR, then writes 12 to that location. ACC remains 12. Finally, fetching HALT advances PC to 4 and execution stops the teaching machine. Four instructions have run.

Branches replace the next address

JUMP 0 puts 0 into PC during execution, regardless of its previous value. JUMPZ 6 jumps only when ACC is zero. If that instruction was fetched from address 4, fetch first makes PC 5. Execution then sets PC to 6 when ACC is zero; otherwise PC stays 5. This is how a sequence can choose a route or repeat a loop.

Interruptions and real processors

At an instruction boundary in this model, the CPU checks for interrupts. To handle one, it saves the PC and other working registers, runs the handler, then restores the saved state. The interrupted program resumes with its own values and next address.

A CPU does not fetch a whole source program at once. It executes machine instructions, often several for one source statement. Modern CPUs overlap and reorder internal work while preserving the program's required results.

Processor performance depends on the work a program needs and how quickly the computer completes that work. Clock speed, useful work per cycle, waiting time and opportunities for parallel work all matter.

Clock speed and a fixed cycle count

For a task requiring a known number of clock cycles:

A task needing 6 billion cycles takes 2 seconds at 3 GHz and 1.5 seconds at 4 GHz. The comparison holds the cycle count fixed. Across different processor designs, a program may need different numbers of cycles. A 3.5 GHz chip can therefore outperform a 4 GHz chip by finishing more useful instructions per cycle.

Higher clock rates also use more power and produce heat. Thermal throttling reduces the clock when a processor gets too hot. This helps explain why performance gains have come from more than raising gigahertz.

Cores divide only the parallel part

Suppose a task takes 10 seconds on one core. Two seconds must happen in sequence; eight seconds can be divided evenly among four cores. Ignoring coordination overhead:

Dividing the whole 10 seconds by four gives 2.5 seconds, but incorrectly divides the sequential work. Even unlimited cores cannot remove those two seconds. Multiple cores also help separate programs run at the same time, even when each program uses only one core.

A pipeline overlaps stages

In a three-stage pipeline, one instruction executes while the next decodes and another fetches. Each instruction still passes through all three stages. The gain is more instructions completed over a period of time.

If each stage takes one cycle, ten independent instructions take 30 cycles without overlap. An ideal pipeline needs three cycles to finish the first instruction and one more for each remaining instruction:

A branch can make instructions already fetched useless. Discarding that work costs cycles, so processors predict branches. Real dependencies and memory waits also keep a pipeline from always reaching its ideal rate.

Keep the processor supplied

A cache holds nearby copies of instructions and data. More useful cache capacity can reduce trips to RAM, especially when a program repeatedly uses a working set that did not fit before. If that working set already fits, extra capacity may help little.

Memory bandwidth limits how fast many values can arrive. Storage speed matters when opening files or starting applications: moving from a hard disk to an SSD can reduce the delay even though the CPU is unchanged. Word size and the instructions a processor supports also affect suitable workloads.

More transistors, different uses

Moore's law describes Gordon Moore's observation, first made in 1965 and revised in 1975, that transistor counts doubled about every two years. This historical trend is not a rule that programs become twice as fast on a fixed schedule. As scaling has slowed, chip designers have used additional transistors for cores, caches, GPUs and specialized accelerators. A useful comparison asks how long the same task takes under the same conditions.

Machine code is binary instructions for a particular kind of processor. Assembly language writes those instructions with readable names. Both describe operations much closer to the hardware than a high-level language such as Python or C.

Operations and operands

An instruction contains an opcode specifying what to do and usually one or more operands specifying what to use. An operand can name a register or memory address, or supply a value directly. Its meaning comes from the instruction's defined format.

Consider an 8-bit teaching encoding. The first four bits hold an opcode; the last four hold an address. If LOAD is 0001, then LOAD 10 becomes 0001 1010, because decimal 10 is binary 1010. Four opcode bits allow $2^4=16$ operation codes. Four address bits name locations 0 through 15. This encoding illustrates a limited format; the other teaching-machine traces use written instructions with larger addresses.

An instruction set architecture (ISA) defines the instructions, encodings and registers a processor offers. x86-64, ARM and RISC-V are examples. ARM's A64 instructions are 32 bits long; x86-64 instructions range from 1 to 15 bytes. A 64-bit processor's word size does not determine every instruction's length.

A readable loop

An assembler turns assembly mnemonics and labels into machine code for an ISA. Useful instruction groups include data transfer, arithmetic and logic, control flow, and system or I/O operations.

This accumulator program counts down from 3. SUB 21 subtracts the contents of address 21. JUMPZ branches if ACC is zero.

0  LOAD 20
1  SUB 21
2  STORE 20
3  JUMPZ 5
4  JUMP 0
5  HALT

20 holds 3; 21 holds 1.

On the first pass, LOAD reads 3, SUB leaves 2, and STORE saves 2. The zero test fails, so JUMP 0 starts another pass. The second pass saves 1 and jumps back. The third saves 0, so JUMPZ 5 goes to HALT.

The first two passes use five instructions each. The last uses four before HALT, which also counts as an instruction: $5+5+4+1=15$. Counting only the six written lines misses repeated executions.

One source statement, several instructions

A high-level statement such as total = price + tax can become operations to load a value, add another and store the result. High-level languages express variables, choices, loops and functions without naming every register. Assembly usually maps each written instruction to one machine instruction and depends closely on its ISA.

Machine code for x86-64 cannot execute natively as ARM code. The source can be recompiled for ARM, or a translation or emulation layer can handle the mismatch.

RISC and CISC

RISC designs such as ARM and RISC-V favor simple, regular instructions. Many use fixed-length instructions, but RISC-V can mix 16-bit compressed forms with standard 32-bit instructions. CISC designs such as x86 offer more complex, variable-length instructions. Modern x86 processors break instructions into simpler internal operations. These labels describe design approaches, not a guarantee that one machine is faster.

Source code is readable program text. A processor executes machine instructions, so a tool must bridge the gap. Compilation and interpretation describe ways to do that; many real implementations combine them.

The translation tools

Most compilers work before a program starts. A just-in-time (JIT) compiler works during execution. An interpreter is itself a machine-code program: the CPU executes the interpreter, which performs the source program's operations.

Follow a C build

The command clang hello.c -o hello builds an executable named hello from hello.c. A build tool such as make can arrange compiler commands for the programmer. The main stages are:

1. Preprocessing: handle directives such as #include <stdio.h>, bringing header declarations into the source.
2. Compiling: translate the C code into assembly-level operations.
3. Assembling: encode those operations as machine code in object files.
4. Linking: connect object code and library references to produce an executable.

Headers describe library interfaces; including a header does not by itself copy the compiled library implementation into the program. Linking supplies the connection to that code. Static linking copies required library code into the executable. Dynamic linking records shared-library dependencies that are loaded and connected when needed.

The executable targets an ISA and an operating-system format. Building for an ARM Mac and an x86-64 Windows computer therefore requires separate native builds. Editing the source also requires rebuilding a compiled executable before the change takes effect.

Errors happen at different stages

A compiler can report syntax errors, such as a missing semicolon in C, and type errors where the language checks types. Successful compilation does not establish that the program solves the right problem. A logic error produces a wrong result. A run-time error occurs while the program executes, such as division by an input value that turns out to be zero.

A simple interpreter may reach an error only after earlier statements have run. Python checks an entire file's syntax first, but an undefined name can still fail only when execution reaches it. The translation method alone does not tell you when every kind of error is found.

Bytecode and virtual machines

Java compiles source into bytecode, instructions for the Java Virtual Machine (JVM). Each supported platform supplies its own JVM. It can interpret bytecode and JIT-compile frequently used sections into the local CPU's machine code. The bytecode stays portable because the platform-specific JVM handles the hardware differences.

CPython also compiles Python into bytecode and executes it with a virtual machine. PyPy uses a JIT compiler, and browser JavaScript engines use JIT compilation too. "Compiled" and "interpreted" describe implementations, not permanent properties of a language.

Ahead-of-time native code usually avoids repeated interpretation work. Interpretation makes an edit-and-run cycle convenient, while bytecode and JIT combine portability with runtime optimization. In every route, the CPU ultimately follows machine instructions, and the OS loads the required executable code into memory.

Main memory holds the instructions and data currently available to the CPU. For an ordinary application stored on an SSD, the OS first brings the needed code and data into RAM. The CPU then fetches instructions through its memory and cache system.

RAM, DRAM and SRAM

RAM means random-access memory: a location can be reached without going through all earlier locations. Normal working RAM is volatile, so its contents are lost without power. Saving a document copies its data to non-volatile storage.

Main memory uses DRAM, which stores bits as charge in small capacitors. The charge leaks, so the cells need refresh, commonly over a 64 ms refresh interval. SRAM uses latch-style transistor circuits that retain their state while powered. It needs no refresh, but uses more space and costs more per bit. Its speed suits processor caches.

ROM, or read-only memory, is non-volatile memory associated with fixed instructions such as firmware. Modern UEFI or BIOS firmware normally lives in updateable flash. A phone's advertised file capacity is flash storage, even when a description informally calls it "ROM"; the phone routinely writes files there.

A byte has an address

In byte-addressable memory, each address names one byte. A 4-byte integer starting at decimal address 1000 occupies locations 1000, 1001, 1002 and 1003. The next unused location is 1004. Addresses are often written in hexadecimal, such as 0x7FFE0010, because hex compactly represents bit patterns.

The address identifies where bytes are found. Reading the number written as an address is different from reading the value stored at that address.

Capacity units use two systems

A byte contains 8 bits. Lowercase b means bits; uppercase B means bytes.

A drive sold as 1 TB contains ${10}^{12}$ bytes. In GiB the count is:

Some operating-system displays label this binary count "GB." The different number follows from the unit size; it is not evidence of missing space.

Capacity is different from processor speed

More RAM lets more running programs and data stay ready at once. When working data exceeds RAM, the OS may move pages to storage, making access slower. Extra RAM helps that shortage but does not raise the CPU's clock speed. Deleting saved files frees storage. Closing unneeded programs or tabs can release working RAM.

Secondary storage keeps programs and files without power. Compared with RAM it offers more capacity at a lower cost per byte, with slower access. Different storage technologies trade speed, cost, portability and durability.

Magnetic disks and solid-state drives

A hard disk drive (HDD) stores magnetic patterns on spinning platters. A moving head seeks the right track, then waits for the desired part of the platter to rotate beneath it. Both movements add access delay.

At 7,200 revolutions per minute, one turn takes:

The average rotational wait is half a turn, about 4.2 ms. This is only the rotational part, not the full read time; seeking and transferring also take time. Moving parts also make a working HDD vulnerable to shocks.

An SSD stores charge in flash cells and has no moving parts. Small random reads take tens of microseconds instead of the milliseconds typical of HDD access. SSDs are quiet, resist shocks and suit portable computers. HDDs generally offer a lower cost per terabyte for large collections.

Flash cells tolerate a limited number of erase/write cycles. The controller uses wear leveling to spread writes across cells. USB flash drives, memory cards and phone storage also use flash, though the controller and interface affect their performance.

Optical discs and tape

Typical capacities are about 700 MB for a CD, 4.7 GB for a single-layer DVD and 25 GB for a single-layer Blu-ray disc. Optical media are portable but slow compared with modern drives.

Tape offers low cost for large archives. Its sequential access means the drive must wind to reach a distant file. Disks and SSDs provide direct access, reaching a selected location without traversing all earlier data. Tape therefore suits scheduled bulk backups better than an application that repeatedly opens scattered small files.

Cloud storage is a service

Cloud storage keeps files on equipment in a provider's data centers. The underlying media are still SSDs, HDDs or tape. A network connection adds access and transfer delays. The service offers sharing, remote access and off-site copies, with ongoing fees and dependence on the provider's access controls and reliability.

Match the limiting factor

Access time is the delay before data starts arriving. Transfer rate measures how quickly it flows afterward. Many small file reads repeatedly pay access delay; one large continuous file puts more emphasis on transfer rate.

An SSD suits a laptop's active programs. HDDs suit a server storing 20 TB of video economically. Tape or a cloud archive suits a company's long-term records, while a USB drive is convenient for carrying files. Choose using capacity, access time, transfer rate, cost per byte, power use, reliability and portability. Being made from chips does not make an SSD into working RAM: it remains non-volatile storage behind a storage controller.

A computer combines several kinds of storage because fast access, large capacity and low cost do not come together in one technology. The memory hierarchy puts a small amount of very fast storage near the CPU and larger, slower stores farther away.

The levels of the hierarchy

From fastest and smallest toward slower and larger, the main levels are registers, L1/L2/L3 cache, RAM, SSD, HDD, and archive storage. Cost per byte generally falls as capacity grows.

These times show scale, not one fixed specification for every device. Using 1 ns for L1, 100 ns for RAM and 10 ms for a disk, RAM takes about 100 times as long as L1 and the disk about 100,000 times as long as RAM.

Hits, misses and useful copies

A CPU cache uses SRAM to hold blocks copied from main memory. Hardware looks through the cache levels before fetching from RAM. A hit finds the requested contents in the cache. A miss requires a slower-level fetch and can bring a copy into the cache.

The hit rate is hits divided by all accesses. For 950 hits in 1,000 accesses, it is 95%. A miss is not missing or damaged data; it means the fast copy was not available.

Why past access predicts future access

Temporal locality means recently used contents are likely to be used again soon. A loop repeatedly reads a counter and its own instructions. Spatial locality means nearby addresses are likely to be used soon. Reading consecutive list elements has this pattern.

A cache brings in a whole cache line, commonly 64 neighboring bytes, taking advantage of spatial locality. Several levels balance capacity with lookup time: one enormous cache would take longer to search.

Compute the average delay

Suppose a cache check takes 1 ns and a RAM access takes 100 ns. A miss costs both, so it takes 101 ns. At a 95% hit rate:

At an 80% hit rate:

The second average is $21÷6=3.5$ times as large. Weight the full hit cost and full miss cost by how often each occurs. Forgetting the cache check on a miss would change this model's answer.

Caching beyond the processor

The OS caches file contents in RAM. A browser caches downloaded web files on storage, and content delivery networks keep copies near users. They all reuse nearby copies to avoid repeated slow retrieval. Clearing a browser cache removes browser files; it does not clear CPU cache circuits. CPU caches hold small memory blocks, not an organized library of whole documents.

An operating system (OS) manages hardware and supplies services to applications. Windows, macOS and Linux serve personal computers and servers; Android and iOS serve mobile devices. The visible desktop is only one part of this work.

Manage resources and hide hardware details

As a resource manager, the OS assigns processor time, working memory, files and devices to programs and users. As an abstraction, it provides simpler operations that hide hardware details. A text editor can request "open the file report.txt" without choosing disk tracks or device commands.

The user interface lets people request this work. A graphical user interface (GUI) uses windows, icons, menus and touch or a pointer. A command-line interface (CLI) accepts typed commands. Commands such as ls on Linux and macOS or dir on Windows list files; scripts can combine commands for repeated tasks.

The kernel controls privileged operations

The kernel is the OS core responsible for hardware control and protected resources. Applications run in user mode with restricted privileges. Kernel code runs in kernel mode with greater privileges. An application requests a protected service through a system call, such as asking the OS to read a file.

The kernel checks permissions and carries out the permitted action. A faulty application cannot simply use a normal user-mode instruction to take control of every device or read another process's protected memory.

Share processor time

The scheduler decides which ready program gets processor time. Short turns on a single processing stream make music playback and document editing appear simultaneous. Multiple cores also allow work to run at the same moment. Some CPUs support hardware multithreading within a core, but time sharing remains necessary when more work is ready than the hardware can execute together.

Give files names and devices drivers

A file system tracks file contents and metadata such as size, dates and permissions. Folders form a hierarchy; a path identifies a file, for example /home/sam/notes.txt on Linux. NTFS, APFS and ext4 are file-system examples.

Deleting a file commonly removes its directory entry and releases its space for reuse. That differs from deliberately overwriting every byte. Old data can sometimes remain recoverable, especially on HDDs; a normal delete is not a secure-erasure guarantee.

A driver translates general device requests into commands a controller understands. Standard drivers handle many keyboards and USB drives, while some devices require a specific driver.

Match software to its role

The OS, drivers and utilities such as backup tools are system software. Browsers, editors, games and spreadsheets are application software. Mobile systems emphasize battery life, touch and app separation; servers support network services. A real-time OS meets specified response deadlines for control tasks. Very simple embedded devices can run one program without a full OS.

Starting a computer and starting an application involve different stages. Startup brings the operating system into control. Application loading then creates a running process that uses the processor, memory and OS services.

Start with persistent instructions

At power-on, working RAM has no usable running program. The CPU begins with firmware stored in non-volatile memory. On a modern PC, UEFI firmware prepares hardware and performs startup checks, often called the power-on self-test (POST). It selects a boot device and starts a bootloader. The bootloader loads the OS kernel into RAM and transfers control to it. The kernel prepares memory management, drivers and services before the login or home screen appears.

Turn a program file into a process

A program is stored instructions. A process is a running instance, with memory, register state and resources. Separate instances of one editor can keep separate documents even though they started from the same program file.

To launch an application, the OS checks the executable and permission to run it, creates an address space, loads the initially needed code and data, sets up a stack and arranges its starting instruction address. More pages can be loaded when used. The scheduler gives the process time on the CPU, which executes its machine instructions.

Different regions hold different contents

Calling a function adds stack information; returning releases that call's part. Repeated calls with no stopping point can exhaust the stack, causing a stack overflow. A memory leak happens when a program keeps memory it no longer needs, causing its retained allocation to grow. Simply using a large amount of memory is not enough to diagnose a leak.

Separate addresses from physical locations

Virtual memory gives each process its own address space. The OS and the CPU's memory management unit (MMU) map virtual addresses to physical RAM in pages, often 4 KiB. Two processes can use 0x1000 for different physical locations. Access permissions stop unauthorized reads or writes; the OS can also explicitly allow shared pages.

A prohibited access causes a fault, which can end the process. On Linux or macOS, a C program may report a "segmentation fault." A virtual address names a location in that process's map, not necessarily an identical numbered byte of RAM.

When memory demand is high, the OS can move inactive pages to a swap or page file on storage. Retrieving an illustrative page in 100 µs takes about 1,000 times a 100 ns RAM access. Repeated page movement, called thrashing, can dominate execution time. Reducing active memory demand or adding RAM can help.

Follow a key press through the layers

A keyboard controller signals an interrupt. The OS handler and driver obtain the event and deliver it to the editor process. The editor updates the document in its memory and asks OS graphics services to update the display. Saving asks the file system to write the document to storage. When the process ends, the OS reclaims its memory and resources. Saved data remains; changes kept only in process memory disappear.