Computer Organization and Architecture Course

Free online course · 6 lessons

Study the hardware and software interface: performance, digital logic, the RISC-V instruction set, computer arithmetic, datapath and pipelining, caches and virtual memory, and parallel processors. After the course you can explain and estimate how code runs on real hardware.

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What you will learn in 6 lessons

Every lesson includes all nine study tools

  • Study Guide
  • Summary
  • Walkthroughs
  • Practice Questions
  • Flashcards
  • Explain It
  • Key Terms
  • Cheat Sheet
  • Concept Map
  1. Explain the layers of abstraction from applications to transistors and measure performance with execution time, CPI, clock rate and Amdahl's law.

    5 learning goals
    1. 1.Describe the layers of a computer system and its hardware/software interface
    2. 2.Define and measure computer performance
    3. 3.Predict execution time with the performance equation
    4. 4.Use Amdahl's law to estimate the benefit of an improvement
    5. 5.Explain the power wall and the shift to multicore processors
  2. Read and write simple RISC-V assembly, and explain how instructions, registers, memory addressing and procedure calls implement high-level code.

    6 learning goals
    1. 1.Describe how instructions, registers and memory operands work
    2. 2.Compute, compare and control the flow of a program
    3. 3.Encode and decode RISC-V machine instructions
    4. 4.Implement procedure calls with registers and the stack
    5. 5.Follow a program from source code to a running process
    6. 6.Compare RISC and CISC instruction set designs
  3. Explain how hardware adds, subtracts, multiplies and divides integers, detects overflow and represents and rounds floating-point numbers.

    5 learning goals
    1. 1.Add and subtract integers and detect overflow
    2. 2.Design an arithmetic logic unit
    3. 3.Multiply and divide integers in hardware
    4. 4.Represent real numbers in IEEE 754 floating point
    5. 5.Compute and round with floating-point numbers
  4. Trace instructions through a single-cycle and a pipelined datapath, and explain how hazards are handled with forwarding, stalls and branch prediction.

    5 learning goals
    1. 1.Build a single-cycle datapath
    2. 2.Design the control unit for the single-cycle processor
    3. 3.Pipeline the datapath
    4. 4.Detect and resolve data hazards
    5. 5.Handle control hazards and predict branches
  5. Explain how caches exploit locality, calculate hit rates and average memory access time and describe how virtual memory and TLBs fit into the hierarchy.

    6 learning goals
    1. 1.Explain why computers use a memory hierarchy
    2. 2.Find data in direct-mapped and set-associative caches
    3. 3.Explain cache misses and write policies
    4. 4.Calculate cache performance
    5. 5.Explain how virtual memory and TLBs fit into the hierarchy
    6. 6.Write cache-aware programs
  6. Compare instruction-, data- and thread-level parallelism, and explain how multicore processors, GPUs and clusters share work and keep memory coherent.

    5 learning goals
    1. 1.Explain where parallelism comes from and how parallel hardware is classified
    2. 2.Predict and measure the limits of parallel speedup
    3. 3.Exploit data-level parallelism with SIMD, vector processors and GPUs
    4. 4.Share memory among cores and keep caches coherent
    5. 5.Explain how clusters and warehouse-scale computers share work over networks

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